1. Field of the Invention
The present invention relates to silicon-controlled rectifier structures and, more particularly, to silicon controlled rectifier structures with reduced turn on times.
2. Description of the Related Art
A silicon-controlled rectifier (SCR) is a device that provides an open circuit between a first node and a second node when the voltage across the first and second nodes is positive and less than a breakdown voltage. When the voltage across the first and second nodes rises to be equal to or greater than the breakdown voltage, the SCR provides a low-resistance current path between the first and second nodes. Further, once the low-resistance current path has been provided, the SCR maintains the current path as long as the voltage across the first and second nodes is equal to or greater than a holding voltage that is lower than the breakdown voltage.
As a result of these characteristics, SCRs have been used to provide electrostatic discharge (ESD) protection. When used for ESD protection, the first node becomes a to-be-protected node, and the second node becomes a grounding node. The SCR operates within an ESD protection window that has a maximum voltage defined by the destructive breakdown level of the to-be-protected node, and a minimum voltage (also known as a latch-up voltage) defined by any DC bias on the to-be-protected node. The breakdown voltage of the SCR is then set to a value that is less than the maximum voltage of the window, while the holding voltage is set to a value that is greater than the minimum voltage of the window.
Thus, when the voltage across the to-be-protected node and the grounding node is less than the breakdown voltage, the SCR provides an open circuit between the to-be-protected node and the grounding node. However, when the to-be-protected node receives a voltage spike that equals or exceeds the breakdown voltage, such as when an ungrounded human-body contact occurs, the SCR provides a low-resistance current path from the to-be-protected node to the grounding node. In addition, once the ESD event has passed and the voltage on the to-be-protected node falls below the holding voltage, the SCR again provides an open circuit between the to-be-protected node and the grounding node.
FIGS. 1A–1B show views that illustrate a prior-art, silicon controlled rectifier (SCR) 100. FIG. 1A shows a plan view of SCR 100, while FIG. 1B shows a cross-sectional view taken along line 1B—1B of FIG. 1A. As shown in FIGS. 1A–1B, SCR 100 has an n− well 112 which is formed in a, p− semiconductor material 110, such as a substrate or a well.
In addition, SCR 100 has a p+ finger region 114 that is formed in n− well 112 to have a first length L1, and an n+ finger region 116 that is formed in n− well 112 to have a second length L2 that is substantially equal to the first length L1. P+ and n+ finger regions 114 and 116, which are parallel to each other and approximately 100 microns in length, are both electrically connected to a to-be-protected node.
SCR 100 further has a trench isolation region STI that includes a first isolation section STI1 that contacts n− well 112 and p+ finger region 114, and a second isolation section STI2 that contacts n− well 112, p+ finger region 114, and n+ finger region 116. In addition, trench isolation region STI also includes a third isolation section STI3 that contacts p− material 110. The first, second, and third isolation sections STI1, STI2, and STI3 are substantially parallel.
As further shown in FIGS. 1A–1B, SCR 100 also has a p+ finger region 122 and an n+ finger region 124 that are formed in p− semiconductor material 110. P+ and n+ finger regions 122 and 124, which have third and fourth lengths L3 and L4, respectively, both contact and are located on opposite sides of the third isolation section STI3.
In addition, n+ finger region 124 contacts the first isolation section STI1. As additionally shown in FIGS. 1A–1B, the first, second, third, and fourth lengths L1, L2, L3, and L4 of p+ finger region 114, n+ finger region 116, p+ finger region 122, and n+ finger region 124, respectively, are substantially equal.
Further, SCR 100 includes a first layer of metal silicide 126A that is formed on p+ finger region 114, a second layer of metal silicide 126B that is formed on n+ finger region 116, a third layer of metal silicide 126C that is formed on p+ finger region 122, and a fourth layer of metal silicide 126D that is formed on n+ finger region 124.
SCR 100 additionally includes a layer of isolation material 128, and a number of contacts 130 that are formed through isolation layer 128 to make electrical connections with p+ finger region 114, n+ finger region 116, p+ finger region 122, and n+ finger region 124. SCR 100 also includes a first metal region 132 that is formed on isolation layer 128 to make an electrical connection with the contacts 130 that are connected to p+ finger region 114 and n+ finger region 116.
SCR 100 further includes a second metal region 134 that is formed on isolation layer 128 to make an electrical connection with the contacts 130 that are connected to p+ finger region 122 and n+ finger region 124. In addition, first metal region 132 is electrically connected to the to-be-protected node, while second metal region 134 is electrically connected to the grounding node.
In operation, when the voltage on metal region 132 is greater than the voltage on metal region 134 by a difference voltage that is less than the breakdown voltage, the voltage reverse biases the junction between n− well 112 and p-type material 110. The reverse-biased junction, in turn, blocks charge carriers from flowing from metal region 132 to metal region 134. However, when the voltage on metal region 132 spikes up to be equal to or greater than the breakdown voltage, the reverse-biased junction breaks down due to avalanche multiplication.
The breakdown of the junction causes a large number of holes to be injected into p− material 110, and a large number of electrons to be injected into n− well 112. The increased number of holes increases the potential of p− material 110 in the region that lies adjacent to n+ region 124, and eventually forward biases the junction between p− material 110 and n+ region 124.
When the increased potential forward biases the junction, a npn transistor, which utilizes n+ region 124 as the emitter, p-type material 110 as the base, and n− well 112 as the collector, turns on. When turned on, n+ (emitter) region 124 injects electrons into (base) material 110. Most of the injected electrons diffuse through (base) material 110 and are swept from (base) material 110 into (collector) n− well 112 by the electric field that extends across the reverse-biased junction. The electrons in (collector) n-well 112 are then collected by n+ region 116.
A small number of the electrons injected into (base) material 110 recombine with holes in (base) material 110 and are lost. The holes lost to recombination with the injected electrons are replaced by holes injected into (base) material 110 by the broken-down reverse-biased junction and, as described below, by the collector current of a pnp transistor, thereby providing the base current.
The electrons that are injected and swept into n− well 112 also decrease the potential of n-well 112 in the region that lies adjacent to p+ region 114, and eventually forward bias the junction between p+ region 114 and n− well 112. When the decreased potential forward biases the junction between p+ region 114 and n− well 112, a pnp transistor formed from p+ region 114, n-well 112, and material 110 turns on.
When turned on, p+ emitter 114 injects holes into base 112. Most of the injected holes diffuse through (base) n− well 112 and are swept from (base) n− well 112 into (collector) material 110 by the electric field that extends across the reverse-biased junction. The holes in (collector) material 110 are then collected by p+ region 122.
A small number of the holes injected into (base) n− well 112 recombine with electrons in (base) n− well 112 and are lost. The electrons lost to recombination with the injected holes are replaced by electrons flowing into n− well 112 as a result of the broken-down reverse-biased junction, and n− well 112 being the collector of the npn transistor. Thus, a small part of the npn collector current forms the base current of the pnp transistor.
Similarly, as noted above, the holes swept into (collector) material 110 also provide the base current holes necessary to compensate for the holes lost to recombination with the diffusing electrons injected by n+ (emitter) region 124. Thus, a small part of the pnp collector current forms the base current of the npn transistor.
Thus, n+ region 124 injects electrons that provide both the electrons for the collector current of the npn transistor as well as the electrons for the base current of the pnp transistor. At the same time, p+ region 114 injects holes that provide both the holes for the collector current of the pnp transistor as well as the holes for the base current of the npn transistor.
One variation of the standard SCR structure, such as SCR 100, is to incorporate an NMOS transistor into SCR 100 to provide low-voltage triggering. FIGS. 2A–2B show views that illustrate a prior-art, low-voltage triggering SCR (LVTSCR) 200. FIG. 2A shows a plan view of LVTSCR 200, while FIG. 2B shows a cross-sectional view taken along line 2B—2B of FIG. 2A. LVRSCR 200 and SCR 100 are similar and, as a result, utilize the same reference numerals to designate the structures that are common to both devices.
As shown in FIGS. 2A–2B, LVTSCR 200 differs from SCR 100 in that LVTSCR 200 has an n+ (floating drain) finger region 210 that is formed in both p− material 110 and n− well 112, and a channel region 212 that is located between n+ (source) finger region 124 and n+ (floating drain) finger region 210. In addition, LVTSCR 200 includes a gate oxide layer 214 that is formed on p− material 110 over channel region 212, a gate 216 that is formed on gate oxide layer 214, and a layer of metal silicide 218 that is formed on n+ finger region 210. N+ (source and drain) finger regions 124 and 210, gate oxide layer 214, gate 216, and metal silicide layer 218 define a NMOS transistor 220 which is typically formed to be identical to the to-be-protected MOS transistors in the circuit.
In operation, when the voltage on the drain of a conventional NMOS transistor spikes up, the drain-to-substrate junction of the NMOS transistor breaks down, for example, at 7 volts, while the gate oxide layer that isolates the gate from the drain destructively breaks down at, for example, 10–15 volts.
Since NMOS transistor 220 is formed to be identical to the to-be-protected MOS transistors, the junction between n+ region 210 and p− material 110 breaks down at the same time that the to-be-protected MOS transistors experience junction break down as a result of an ESD pulse. Once the reverse-biased junction between n+ region 210 and p− material 110 breaks down, the break down triggers LVRSCR 200 to operate the same as SCR 100.
Since junction break down occurs before the MOS transistors experience destructive gate oxide break down, LVTSCR 200 turns on before destructive gate oxide breakdown occurs, thereby protecting the MOS transistors. Thus, the junction break down voltage, which is less than the voltage level that causes destructive gate oxide break down, functions as the breakdown voltage.
In addition, other techniques, such as reducing the width of channel region 212, can be used to lower the breakdown voltage so that the n+ region 210 to p− material 110 junction breaks down before the to-be-protected MOS transistors experience junction break down. Thus, LVTSCR 200 provides a SCR with a significantly lower turn on voltage that allows MOS transistors to be protected from ESD events.
In addition to SCR 100 and LVRSCR 200, another well known SCR type structure is a bipolar SCR (BSCR). FIGS. 3A–3B show views that illustrate a prior-art, bipolar SCR (BSCR) 300. FIG. 3A shows a plan view of BSCR 300, while FIG. 3B shows a cross-sectional view taken along line 3B—3B of FIG. 3A.
As shown in FIGS. 3A–3B, BSCR 300 includes a p− substrate 310, an n+ buried layer 312 that is formed in the top surface of substrate 310, and an n− epitaxial layer 314 that is formed on the top surface of substrate 310. BSCR 300 further has a trench isolation region STI that includes a first isolation section STI1, a second isolation section STI2, and a third isolation section STI3 that are formed in, and contact, n− epitaxial layer 314. The first, second, and third isolation sections STI1, STI2, and STI3 are spaced-apart and substantially parallel.
In addition, BSCR 300 includes a p− base finger region 316 that is formed in the top surface of epitaxial layer 314 to have a first length L1, and a p+ surface finger region 320 that is formed in the top surface of epitaxial layer 314 to have a second length L2 that is substantially equal to the first length L1. BSCR 300 also includes an n+ sinker finger region 322 that is formed in epitaxial layer 314 to have a third length L3 that is substantially equal to the first and second lengths L1 and L2.
BSCR 300 further includes an n+ polysilicon emitter region 324 that is formed on and along a region of the top surface of p− base region 316. In addition, outdiffusion from n+ emitter region 324 forms a small n+ region 326 in the top surface of p− base region 316. In addition, BSCR 300 includes a first metal silicide layer 328A that is formed on and along an edge of p-base region 316, a second metal silicide layer 328B that is formed on p+ surface finger region 320, a third metal silicide layer 328C that is formed on n+ sinker finger region 322, and a fourth metal silicide layer 328D that is formed on polysilicon emitter region 324.
BSCR 300 also includes a layer of isolation material 332 that is formed over epitaxial layer 314, and a plurality of contacts 334 that are formed through isolation layer 332 to make an electrical connection with p− base region 316 via metal silicide layer 328A, p+ surface finger region 320 via metal silicide layer 328B, n+ sinker finger region 322 via metal silicide layer 328C, and n+ poly emitter region 324 via metal silicide layer 328D.
Further, a first metal region 340, which can function as the anode of an ESD diode structure (where the anode is connected to a to-be-protected device, such as the gate of a MOS transistor), is formed on isolation layer 332 to make an electrical connection with the contacts 334 that are electrically connected to p+ surface finger region 320 and n+ sinker finger region 322.
In addition, a second metal region 342, which can function as the cathode of the ESD diode structure (where the cathode is connected to a grounding node), is formed on isolation layer 332 to make an electrical connection with the contacts 334 that are electrically connected to n+ poly emitter region 324. A third metal region 344, which can be resistively connected to second metal region 342, is formed on isolation layer 332 to make an electrical connection with the contacts 334 that are electrically connected to p− base region 316.
BSCR 300 forms an npn bipolar transistor that utilizes n+ region 326 as the emitter, p− base region 316 as the base, and n+ buried layer 312, n− epitaxial layer 314, and n+ sinker finger region 322 as the collector. BSCR 300 also forms a pnp transistor that utilizes p+ surface finger region 320 as the emitter, n+ buried layer 312 and n− epitaxial layer 314 as the base, and p− base region 316 as the collector.
In operation, when a voltage on the anode of BSCR 300 rises with respect to the voltage on the cathode, the voltage on n+ sinker finger region 322 and n− epitaxial layer 314 rises with respect to the voltage on p− base region 316, thereby reverse biasing the pn junction between p− base region 316 and n− epitaxial layer 314. As a result, BSCR 300 blocks a current, other than a leakage current, from flowing from the anode to the cathode until the anode-to-cathode voltage exceeds a breakdown voltage.
When the rising voltage on the anode exceeds the breakdown voltage, avalanche multiplication causes large numbers of electrons to be injected into n− epitaxial layer 314 and large numbers of holes to be injected into p− base region 316. The electrons injected into n− epitaxial layer 314 follow a current path through n− epitaxial layer 314, n+ buried layer 312, and n+ sinker region 322.
The increased number of electrons in n− epitaxial layer 314 reduces the potential at the pn junction between p+ surface finger region 320 and n− epitaxial layer 314 which, in turn, forward biases the pn junction between p+ surface finger region 320 and n− epitaxial layer 314, thereby allowing p+ surface finger region 320 to inject holes into n− epitaxial layer 314.
In addition, the holes injected into p− base region 316 increase the potential in p− base region 316 which, in turn, forward biases the pn junction between p− base region 316 and n+ emitter region 326. When forward biased, n+ emitter region 326 injects electrons into p− base region 316.
Further, the accumulation of positive charge in p− base region 316, and the accumulation of negative charge in n− epitaxial layer 314 due to the injection of large numbers of holes and electrons, respectively, reduces the magnitude of the reversed biased junction until the pn junction between p− base region 316, and n− epitaxial layer 314 switches and becomes forward biased. Once the pn junction between p− base region 316 and n− epitaxial layer 314 becomes forward biased, a large current flows from the anode to the cathode, while the anode-to-cathode voltage drops to a holding voltage that is substantially lower than the breakdown voltage.
One problem with large SCR structures, such as SCR 100, LVTSCR 200, and BSCR 300, is that it takes a reasonably long time to turn these structures on due to the capacitance associated with the structures. Thus, there is a need for a large SCR structure that has a reduced turn on time.